1. Field of the Invention
This invention relates to semiconductor devices and, more particularly, to a vertical power MOSFET.
2. Description of the Prior Art
Power MOSFETS frequently are used in high speed switching applications where their superior frequency response and switching speed can be best utilized. While the advantages offered by MOSFETS are well known, some performance detriments have been identified and must be overcome for MOSFETS to continue to remain as an attractive power switching device.
One problem with vertical power MOSFETS is the existence of a relatively high on-state voltage drop as a result of high on-state resistance. Among other things, the on-state resistance for a specified silicon area (hereinafter referred to as the "specific on-resistance") is determined by the resistivity and thickness of the epitaxial layer. Since the epitaxial layer characteristics also determine the breakdown voltage of the device, high voltage power MOSFETS have inherently higher specific on-resistance than do low voltage power MOSFETS. Furthermore, unlike bipolar transistors, the resistivity of the MOSFET drain region is not modulated by minority carrier injection. Consequently, high voltage MOSFETS have a higher specific on-resistance compared to bipolar transistors with similar die size and breakdown voltage rating. To offset the resistance advantage that high voltage bipolar transistors enjoy over power MOSFETS, improvements in the specific on-resistance are needed.
The size of the MOSFET cell, which forms the source and channel regions has been shown to have a dramatic effect on the specific on-resistance. The smaller the size of the cell, the lower the specific on-resistance. Unfortunately, cell pitch has been limited to about 16 micrometers using conventional methods, i.e., projection photolithography, plasma etching, and furnace dopant diffusion. This is a result of the required alignment tolerances of the photolithographic and etching processes, as well as lateral diffusion of the dopant impurities in the diffusion process. Alignment tolerances may be reduced by employing higher resolution equipment, but the only practical way to reduce lateral encroachment of the dopant impurities is to reduce the vertical junction depth. Unfortunately, junction depth cannot be reduced indiscriminately without degrading the durability of the device. Accordingly, the search for smaller MOSFET cells has driven power MOSFET manufacturers to employ more sophisticated equipment and processing methods with the added costs involved.
Another problem with conventional MOSFET devices is that they include a source region which acts with the body diode to form a parasitic transistor. In such a parasitic device the source region acts as the emitter, the channel body lying between the source and drain acts as the base, and the epitaxial layer forming the drain acts as the collector. The transistor is undesirable because its inadvertent activation can lead to destruction of the MOSFET.
Although the common uses of power MOSFETS are not affected by the parasitic transistor, certain modes of operation, such as unclamped inductive load switching and large dV/dt operation, can cause inadvertent activation. During unclamped inductive load switching, the MOSFET attempts to switch off the current, but the inductor resisting the change continues to force the current through the reverse biased MOSFET in an avalanche mode. A portion of this avalanche current flows through the base of the parasitic transistor. If the current is large enough and the base sheet resistance is high enough, the induced voltage drop in the base can exceed the base/emitter turn-on voltage and the parasitic transistor turns on. Similarly, during switching and other large dV/dt conditions, the charging and discharging of the PN body diode junction capacitance causes portions of the charging current to flow through the base of the parasitic transistor and, if large enough, can cause the parasitic transistor to turn on. Thus, the parasitic transistor limits the ability of a MOSFET to withstand high currents in the avalanche mode and large dV/dt conditions.
To avoid the activation condition, either the current in the base of the parasitic device must be limited, which usually is not possible in the foregoing situations, or the base spreading resistance must be minimized. One method of reducing the base spreading resistance e.g., in N-channel devices, is to add a low resistivity p-type region in the center of the cell. The p.sup.+ region effectively shorts out part of the base of the parasitic transistor, preventing the parasitic transistor from turning on. However, the accuracy of the placement of the p.sup.+ region in relation to the outside edge of the source region, as well as the length of the source region, is critical and difficult to control using conventional methods.
Finally, a large number of masking and diffusion steps ordinarily are required when manufacturing MOSFETS, and this increases the number of defects introduced during the manufacturing process. Defects generally cause device failure and reduced yield, i.e., the number of acceptable device formed on a wafer during the manufacturing process. This, of course, increases the cost of individual devices because a substantial portion of cost of devices is the semiconductor wafer in which the devices are formed.